Memory is an important aspect of processor design. As is well known, processors are often used in conjunction with a memory system that includes a hierarchy of different storage elements. For example, such a memory system may include a backing store, a main memory and a cache memory, as described in, e.g., M. J. Flynn, “Computer Architecture: Pipelined and Parallel Processor Design,” Jones and Bartlett Publishers, Boston, Mass., 1995, which is incorporated by reference herein.
Memory performance is typically characterized by parameters such as access time and bandwidth. The access time refers to the time between a processor request for a particular piece of data from memory and the return of the requested data to the processor. The memory bandwidth refers to the number of memory access requests that can be accommodated by the memory per unit of time.
A given memory, such as the cache memory or main memory in the above-noted illustrative memory system configuration, may be organized in the form of multiple banks. Portions of the memory may also be referred to as modules. For example, a number of banks may be combined into a single memory module, or a number of modules may be combined to form one of the banks. Typically, only a subset of the banks of the memory may be active at any given time during a memory access. In the simplest possible arrangement, a single processor makes a request to a single memory module. The processor then ceases activity and waits for service from the module. When the module responds, the processor activity resumes.
Each memory module has at least two important parameters, namely, module access time and module cycle time. The module access time is the time required to retrieve data into an output memory buffer register given a valid address. Module cycle time is the minimum time between requests directed at the same module.
Historically, processors and memory were separately packaged. However, with modern integration techniques it is possible to integrate multiple modules and banks within a single integrated circuit die along with the processor.
A significant problem with conventional memory access techniques is that such techniques are generally not optimized for use with multithreaded processors, that is, processors which support simultaneous execution of multiple distinct instruction sequences or “threads.” For example, conventional memory access techniques when applied to multithreaded processors often require an excessive number of read and write ports, which unduly increases power consumption. In addition, such techniques when applied to multithreaded processors can result in the stalling of particular processor threads, and increased memory access times.
As is apparent from the foregoing, a need exists for improved memory access techniques for use in conjunction with a memory associated with a multithreaded processor.